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Boolean satisfiability on a graphics processor.

, and . ACM Great Lakes Symposium on VLSI, page 123-126. ACM, (2010)

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Efficient don't care computation for hierarchical designs., , and . ISCAS, IEEE, (2006)Robust window-based multi-node technology-independent logic minimization., , and . ACM Great Lakes Symposium on VLSI, page 357-362. ACM, (2009)Fault table generation using Graphics Processing Units., and . HLDVT, page 60-67. IEEE Computer Society, (2009)A design flow to optimize circuit delay by using standard cells and PLAs., , , , , and . ACM Great Lakes Symposium on VLSI, page 217-222. ACM, (2006)Boolean satisfiability on a graphics processor., and . ACM Great Lakes Symposium on VLSI, page 123-126. ACM, (2010)Highly parallel decoding of space-time codes on graphics processing units., , , , and . Allerton, page 1262-1269. IEEE, (2009)Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation., , and . ISCAS, page 2225-2228. IEEE, (2009)On-chip bidirectional wiring for heavily pipelined systems using network coding., , , and . ICCD, page 131-136. IEEE Computer Society, (2009)Low power and high performance sram design using bank-based selective forward body bias., , , and . ACM Great Lakes Symposium on VLSI, page 441-444. ACM, (2009)Improving FPGA routability using network coding., and . ACM Great Lakes Symposium on VLSI, page 147-150. ACM, (2008)