Author of the publication

20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers.

, , , , and . ISSCC, page 356-357. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Binary Access Memory: An optimized lookup table for successive approximation applications., , , , and . ISCAS, page 1620-1623. IEEE, (2011)The effect of correlated level shifting on noise performance in switched capacitor circuits., , , and . ISCAS, page 942-945. IEEE, (2012)Parallel gain enhancement technique for switched-capacitor circuits., , , , , , and . CICC, page 1-4. IEEE, (2013)An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power., , , , and . ESSCIRC, page 176-179. IEEE, (2015)A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers., , , , and . IEEE J. Solid State Circuits, 54 (3): 646-658 (2019)A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion., , , , , , and . ISSCC, page 58-60. IEEE, (2019)Asynchronous CLS for Zero Crossing based Circuits., , and . ICECS, page 1025-1028. IEEE, (2010)A multiplexer-based digital passive linear counter (PLINCO)., , , and . ICECS, page 607-610. IEEE, (2009)A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion., , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2360-2374 (2021)A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration., , , and . CICC, page 1-2. IEEE, (2023)