Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Venkatram, Hariprasath
add a person with the name Venkatram, Hariprasath
 

Other publications of authors with the same name

Blind background calibration of harmonic distortion based on selective sampling., , , , and . CICC, page 1-4. IEEE, (2013)Parallel gain enhancement technique for switched-capacitor circuits., , , , , , and . CICC, page 1-4. IEEE, (2013)Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling., , , , and . IEEE J. Solid State Circuits, 49 (8): 1715-1724 (2014)A Continuous-Time ΔΣ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (11): 1063-1067 (2015)Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm., , , and . ISCAS, page 2361-2364. IEEE, (2012)Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits., , , and . ISCAS, page 428-431. IEEE, (2012)Correlated jitter sampling for jitter cancellation in pipelined TDC., , , and . ISCAS, page 810-813. IEEE, (2012)Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters., , , , and . ICECS, page 421-424. IEEE, (2015)A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier., , , , and . VLSIC, page 1-2. IEEE, (2014)A 10b Ternary SAR ADC with decision time quantization based redundancy., , , , and . A-SSCC, page 65-68. IEEE, (2011)