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Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors., , , , , , and . HPCC, page 491-496. IEEE, (2010)Introducing Drowsy Technique to Cache Line Usage Predictors., , and . WSCAD, page 259-265. IEEE, (2018)Operand size reconfiguration for big data processing in memory., , , , , and . DATE, page 710-715. IEEE, (2017)SAPIVe: Simple AVX to PIM Vectorizer., , , and . SBESC, page 1-8. IEEE, (2022)TLP and ILP exploitation through a reconfigurable multiprocessor system., , , , , , , and . IPDPS Workshops, page 1-8. IEEE, (2010)Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency., , , , and . PDP, page 388-392. IEEE Computer Society, (2016)Optimizing Memory Locality Using a Locality-Aware Page Table., , , , and . SBAC-PAD, page 198-205. IEEE Computer Society, (2014)Evaluating Dead Line Predictors Efficiency with Drowsy Technique., , and . SBESC, page 250-255. IEEE, (2018)SiNUCA: A Validated Micro-Architecture Simulator., , , , and . HPCC/CSS/ICESS, page 605-610. IEEE, (2015)A Compiler for Automatic Selection of Suitable Processing-in-Memory Instructions., , , , , , and . DATE, page 564-569. IEEE, (2019)