( en | de | ru )

 

Disambiguation of "Cho, Sung-Yong"

Author of the publication

copydeleteadd this publication to your clipboard
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.

, , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (9): 1393-1403 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sung-Yong Cho

Sung-Jun Cho

Sung-bok Cho

Gyu-Sung Cho

Sung-Hyun Cho

 

Other publications of authors with the same name

Convolutional-Neural-Network-Based Partial Discharge Diagnosis for Power Transformer Using UHF Sensor., , , , and . IEEE Access, (2020)A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (9): 1393-1403 (2016)An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (12): 1819-1823 (2018)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology., , , , , and . IEEE J. Solid State Circuits, 54 (10): 2812-2822 (2019)13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration., , , , , , , , , and 25 other author(s). ISSCC, page 242-244. IEEE, (2024)A theoretical analysis of phase shift in pulse injection-locked oscillators., , , , , and . ISCAS, page 1662-1665. IEEE, (2016)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , and . A-SSCC, page 73-76. IEEE, (2018)A new micro biological cell injection system., and . IROS, page 1642-1647. IEEE, (2004)7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers., , , , , , , , , and 20 other author(s). ISSCC, page 130-131. IEEE, (2016)Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH., , , , , , , , , and . VLSIC, page 136-137. IEEE, (2012)