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A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation., , , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1735-1739 (2020)0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link., , , , , , и . ESSCIRC, стр. 475-478. IEEE, (2021)A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2691-2702 (2018)A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection., , , , , , , , , и . ESSCIRC, стр. 384-387. IEEE, (2015)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , и . A-SSCC, стр. 73-76. IEEE, (2018)A theoretical analysis of phase shift in pulse injection-locked oscillators., , , , , и . ISCAS, стр. 1662-1665. IEEE, (2016)A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS., , , , , , и . ISSCC, стр. 410-411. IEEE, (2023)A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop., , , , , , , , и . VLSI Circuits, стр. 94-. IEEE, (2019)Reference Spur Reduction Techniques for a Phase-Locked Loop., , , и . IEEE Access, (2019)6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS., , , и . ISSCC, стр. 124-126. IEEE, (2020)