( en | de | ru )

 

Disambiguation of "Shanbhag, Naresh R."

Author of the publication

copydeleteadd this publication to your clipboard
Low-power distributed arithmetic architectures using nonuniform memory partitioning.

, , and . ISCAS (3), page 470-473. IEEE, (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

Other publications of authors with the same name

Noise-tolerant dynamic circuit design., and . ISCAS (1), page 549-552. IEEE, (1999)Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC., , , and . ISCAS, page 380-383. IEEE, (2008)Roundoff error analysis of the pipelined ADPCM coder., and . ISCAS, page 886-889. IEEE, (1993)Pipelined Adaptive IIR Filter Architecture., and . ISCAS, page 558-561. IEEE, (1995)A pipelined adaptive NEXT canceller., and . IEEE Trans. Signal Process., 46 (8): 2252-2258 (1998)A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , and . IEEE J. Solid State Circuits, 53 (11): 3163-3173 (2018)Area-efficient high-throughput MAP decoder architectures., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 921-933 (2005)Analytical estimation of signal transition activity from word-level statistics., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (7): 718-733 (1997)A voltage overscaled low-power digital filter IC., and . IEEE J. Solid State Circuits, 39 (2): 388-391 (2004)Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing., , and . Proc. IEEE, 108 (12): 2251-2275 (2020)