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Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band., , , и . ISSCC, стр. 50-51. IEEE, (2010)Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 200-204 (2011)Time-to-digital converter with 3-ps resolution and digital linearization algorithm., , , , и . ESSCIRC, стр. 262-265. IEEE, (2010)A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique., , и . ISCAS, стр. 1-4. IEEE, (2018)Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers., , , , , и . ISCAS, стр. 1-4. IEEE, (2018)A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters., , , , , , , , и . NEWCAS, стр. 20-24. IEEE, (2022)2.9 A Background calibration technique to control bandwidth in digital PLLs., , , и . ISSCC, стр. 54-55. IEEE, (2014)10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM., , , , , , , и . ISSCC, стр. 188-190. IEEE, (2024)Phase noise and accuracy in quadrature oscillators., , , , и . ISCAS (1), стр. 161-164. IEEE, (2004)Fast-switching analog PLL with finite-impulse response., , , и . ISCAS (4), стр. 165-168. IEEE, (2004)