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Improved weight assignment for logic switching activity during at-speed test pattern generation.

, , , , , and . ASP-DAC, page 493-498. IEEE, (2010)

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On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs., , , and . ETS, page 1-2. IEEE, (2014)Emulating and diagnosing IR-drop by using dynamic SDF., , , , and . ASP-DAC, page 511-516. IEEE, (2010)Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis., , , , , , , , , and 1 other author(s). ITC, page 1-9. IEEE Computer Society, (2006)Diagnosis with Limited Failure Information., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)Programmable Scan-Based Logic Built-In Self Test., , and . ATS, page 371-377. IEEE, (2007)On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation., , , and . ATS, page 103-108. IEEE, (2021)Interconnect Open Defect Diagnosis with Physical Information., , and . ATS, page 203-209. IEEE, (2006)Improve speed path identification with suspect path expressions., , , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Diagnosing timing related cell internal defects for FinFET technology., , , , and . VLSI-DAT, page 1-4. IEEE, (2015)Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator., , and . DAC, page 535-540. IEEE Computer Society Press, (1990)