( en | de | ru )

 

Disambiguation of "Jung, Tae-Sung"

Author of the publication

copydeleteadd this publication to your clipboard
An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS).

, , , and . IEEE J. Solid State Circuits, 33 (11): 1758-1762 (1998)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tae-Gyu Sung

Jung Sung

See-Jung Sung

Sung-Uk Jung

Chul-Sung Jung

 

Other publications of authors with the same name

SPDBS: An SBML-Based Biochemical Pathway Database System., , , , , , and . ICIC (3), volume 4115 of Lecture Notes in Computer Science, page 543-550. Springer, (2006)PESTAS: a web server for EST analysis and sequence mining., , , , , , , and . Bioinform., 25 (14): 1846-1848 (2009)13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique., , , , , , , , , and 20 other author(s). ISSCC, page 220-221. IEEE, (2020)SPDBSW: A Service Prototype of SPDBS on the Web., and . BNCOD, volume 4587 of Lecture Notes in Computer Science, page 49-57. Springer, (2007)A 4-way pipelined processing architecture for three-step search block-matching motion estimation., and . IEEE Trans. Consumer Electronics, 50 (2): 674-681 (2004)An Efficient OLAP Query Processing Technique Using Measure Attribute Indexes., , and . WISE, volume 3306 of Lecture Notes in Computer Science, page 218-228. Springer, (2004)G-BLAST: BLAST Manager in an Heterogeneous Distributed Environment., , , , , , , , and . TASE, page 315-316. IEEE Computer Society, (2009)A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator., , , , , , and . ISCAS (5), page 81-84. IEEE, (2001)Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs., , , and . ISCAS, page 1211-1214. IEEE, (1995)A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology., , , , , , , , , and 19 other author(s). ISSCC, page 212-213. IEEE, (2011)