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History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.

, , , , , , , , , и . ICS, стр. 251-261. ACM, (2015)

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Другие публикации лиц с тем же именем

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product., , , , , , , , , и 6 other автор(ы). ISCA, стр. 43-56. IEEE, (2021)History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures., , , , , , , , , и . ICS, стр. 251-261. ACM, (2015)A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process., , , , , , , , , и 37 other автор(ы). ISSCC, стр. 448-450. IEEE, (2022)Row-buffer decoupling: A case for low-latency DRAM microarchitecture., , , и . ISCA, стр. 337-348. IEEE Computer Society, (2014)Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices., , , , , , , , , и 2 other автор(ы). HPCA, стр. 61-72. IEEE Computer Society, (2017)McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling., , , и . ISPASS, стр. 74-85. IEEE Computer Society, (2013)Reducing memory access latency with asymmetric DRAM bank organizations., , , , и . ISCA, стр. 380-391. ACM, (2013)3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions., , , , , , , , , и . PACT, стр. 22:1-22:12. ACM, (2018)Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems., , , , , , , и . SC, стр. 1059-1070. IEEE Computer Society, (2014)CiDRA: A cache-inspired DRAM resilience architecture., , , , , и . HPCA, стр. 502-513. IEEE Computer Society, (2015)