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Disambiguation of "Chattopadhyay, Anupam"

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Design and analysis of layered coarse-grained reconfigurable architecture.

, , and . ReConFig, page 1-6. IEEE, (2012)

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Anupam Chattopadhyay

Anupam Singh

Anupam Karmakar

Anupam Sengupta

Dhrupadi Chattopadhyay

 

Other publications of authors with the same name

SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection., , and . HPSR, page 164-170. IEEE, (2013)Design and analysis of layered coarse-grained reconfigurable architecture., , and . ReConFig, page 1-6. IEEE, (2012)Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays., , and . VLSI-SoC, page 1-6. IEEE, (2016)Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks., , , , and . DATE, page 561-564. IEEE, (2021)A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion., , and . VLSI-SoC, page 1-6. IEEE, (2023)Efficient Hardware Accelerator for AEGIS-128 Authenticated Encryption., and . Inscrypt, volume 8957 of Lecture Notes in Computer Science, page 385-402. Springer, (2014)On Threat of Hardware Trojan to Post-Quantum Lattice-Based Schemes: A Key Recovery Attack on SABER and Beyond., , , , , and . SPACE, volume 13162 of Lecture Notes in Computer Science, page 81-103. Springer, (2021)Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs., , , , , and . ASP-DAC, page 449-454. ACM, (2023)Towards Designing a Secure RISC-V System-on-Chip: ITUS., , , , , , and . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization., , , , , and . IEEE Trans. Parallel Distributed Syst., 29 (8): 1707-1720 (2018)