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7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip.

H. Kim, J. Lim, J. Lee, D. Na, J. Shin, C. Kim, S. Yu, J. Shin, S. Lee, D. Rajagopal, S. Kim, K. Kang, J. Park, Y. Kwon, M. Lee, S. Kim, S. Shin, H. Kim, J. Kim, K. Kim, H. Joo, C. Park, J. Kim, M. Lee, D. Kim, H. Yang, D. Byeon, K. Park, K. Kyung, and J. Choi. ISSCC, page 1-3. IEEE, (2015)

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Kyoo-Sik Lee

Myung-Seon Lee

Seon-Guan Lee

Hyo-Seon Lee

Seon Mi Lee

Other publications of authors with the same name

A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition.S. Lee, Y. Kim, H. Park, and J. Sim. J. Electr. Comput. Eng., (2011)A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface.S. Lee, S. Park, H. Park, and J. Sim. IEEE J. Solid State Circuits, 46 (3): 651-659 (2011)A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.D. Na, J. Lee, S. Lee, H. Cho, J. Lee, M. Yang, E. Song, A. Kavala, T. Kim, D. Jang and 12 other author(s). IEEE J. Solid State Circuits, 56 (4): 1129-1140 (2021)A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS.S. Lee, Y. Seo, H. Park, and J. Sim. IEEE J. Solid State Circuits, 45 (12): 2874-2881 (2010)A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS.Y. Seo, S. Lee, and J. Sim. IEEE Trans. Circuits Syst. II Express Briefs, 58-II (2): 70-74 (2011)A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation.H. Ha, S. Lee, B. Kim, H. Park, and J. Sim. IEEE Trans. Circuits Syst. II Express Briefs, 61-II (11): 840-844 (2014)A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling.H. Ha, Y. Suh, S. Lee, H. Park, and J. Sim. CICC, page 1-4. IEEE, (2012)A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL.Y. Kim, S. Lee, H. Park, and J. Sim. IEEE J. Solid State Circuits, 46 (2): 435-444 (2011)A 95fJ/b current-mode transceiver for 10mm on-chip interconnect.S. Lee, S. Lee, D. Sylvester, D. Blaauw, and J. Sim. ISSCC, page 262-263. IEEE, (2013)A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation.S. Lee, H. Ha, H. Park, and J. Sim. ISSCC, page 140-142. IEEE, (2012)

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Disambiguation of "Lee, Seon-Kyoo"

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7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip.

Please choose a person to relate this publication to

Kyoo-Sik Lee

Myung-Seon Lee

Seon-Guan Lee

Hyo-Seon Lee

Seon Mi Lee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lee, Seon-Kyoo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip.

Please choose a person to relate this publication to

Kyoo-Sik Lee

Myung-Seon Lee

Seon-Guan Lee

Hyo-Seon Lee

Seon Mi Lee

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip.