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A 675 Mbps, 4 × 4 64-QAM K-Best MIMO Detector in 0.13 µm CMOS., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 135-147 (2012)A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing., , and . ISCAS, page 1147-1150. IEEE, (2014)VLSI implementation of a hardware-optimized lattice reduction algorithm for WiMAX/LTE MIMO detection., , and . ISCAS, page 3541-3544. IEEE, (2010)A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO detector., and . ISSCC, page 256-257. IEEE, (2009)Non-invasive blood pressure estimation using phonocardiogram., , and . ISCAS, page 1-4. IEEE, (2017)A pipelined scalable high-throughput implementation of a near-ML K-best complex lattice decoder., , and . ICASSP, page 3173-3176. IEEE, (2008)An efficient architecture for distributed resampling for high-speed particle filtering., and . ISCAS, IEEE, (2006)A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 µm CMOS., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (2): 327-340 (2013)Cuff-less high-accuracy calibration-free blood pressure estimation using pulse transit time., , , and . ISCAS, page 1006-1009. IEEE, (2015)An efficient max-log MAP algorithm for VLSI implementation of turbo decoders., and . ISCAS, page 1794-1797. IEEE, (2015)