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Hardware Efficient Approximate Adder Design., and . TENCON, page 806-810. IEEE, (2018)Comments on "Dual-rail asynchronous logic multi-level implementation".. CoRR, (2018)An enhanced sentiment dictionary for domain adaptation with multi-domain dataset in Tamil language (ESD-DA)., , and . Soft Comput., 25 (5): 3697-3711 (2021)Approximate quasi-delay-insensitive asynchronous adders: Design and analysis., , and . MWSCAS, page 1196-1199. IEEE, (2017)Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications., , and . EECS, page 37-44. IEEE, (2019)Self-timed full adder designs based on hybrid input encoding., , and . DDECS, page 56-61. IEEE Computer Society, (2009)A New Design Technique for Weakly Indicating Function Blocks., and . DDECS, page 116-121. IEEE Computer Society, (2008)Theoretical Estimation of the Microalgal Potential for Biofuel Production and Carbon Dioxide Sequestration in India., , , and . SocProS (1), volume 816 of Advances in Intelligent Systems and Computing, page 775-790. Springer, (2017)Dual-Sum Single-Carry Self-Timed Adder Designs., and . ISVLSI, page 121-126. IEEE Computer Society, (2009)A study on the impact of macroeconomic factors on S&P BSE Bankex returns., and . ICACCI, page 2614-2618. IEEE, (2016)