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Disambiguation of "Fukuoka, Kazuki"

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A technique for high-speed circuits on SOI using look-ahead type active body bias control.

, , , , , and . ISCAS (2), page 405-408. IEEE, (2004)

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Leakage power reduction for clock gating scheme on PD-SOI., , , , and . ISCAS (2), page 613-616. IEEE, (2004)A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2012)10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores., , , , , , , , , and 4 other author(s). ISSCC, page 178-179. IEEE, (2014)A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power., , , , , , , and . ISSCC, page 240-241. IEEE, (2023)Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor., , , , , , , , , and 3 other author(s). CICC, page 1-4. IEEE, (2013)4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability., , , , , , , and . ISSCC, page 80-81. IEEE, (2016)A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 423-432. Springer, (2004)Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 364-372 (2016)A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor., , , , , , , , , and 5 other author(s). ISSCC, page 156-157. IEEE, (2013)A 28nm fully digital voltage monitor with 16.5uV/°C accuracy and 0.8mV quantized error from -40 to 160°C for ISO26262 ASIL-D capable MCU., , and . A-SSCC, page 129-132. IEEE, (2019)