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A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories.

, , and . MOCAST, page 1-4. IEEE, (2023)

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Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits., and . Journal of Circuits, Systems, and Computers, 25 (11): 1650142:1-1650142:17 (2016)Hyper Dimensional Computing with Ferroelectric Tunneling Junctions., , , , , and . NANOARCH, page 3:1-3:2. ACM, (2023)Direct state transfer in MLC based memristive ReRAM devices for ternary computing., and . ECCTD, page 1-5. IEEE, (2020)A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM., and . NORCAS, page 1-6. IEEE, (2019)Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles., and . ISVLSI, page 157-163. IEEE, (2021)Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic., , and . ICECS, page 1-6. IEEE, (2021)Memristive logic: A framework for evaluation and comparison., , , , , , and . PATMOS, page 1-8. IEEE, (2017)A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (3): 1148-1158 (2022)A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories., , and . MOCAST, page 1-4. IEEE, (2023)On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory., , , and . NorCAS, page 1-6. IEEE, (2024)