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Disambiguation of "Ionescu, Adrian M."

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Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (11): 2053-2067 (2008)

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Claudia Ionescu

Andra Ionescu

Catalin Ionescu

Radu Ionescu

Ursula Ionescu

 

Other publications of authors with the same name

A SET quantizer circuit aiming at digital communication system., , , and . ISCAS (5), page 860-863. IEEE, (2002)Few electron devices: towards hybrid CMOS-SET integrated circuits., , , , and . DAC, page 88-93. ACM, (2002)Compact modeling of homojunction tunnel FETs., , , , , , and . MIXDES, page 54-57. IEEE, (2014)Model-Based ISO 14971 Risk Management of EEG-Based Medical Devices., , , and . EMBC, page 1-7. IEEE, (2023)Complementary black phosphorous FETs by workfunction engineering of pre-patterned Au and Ag embedded electrodes., , , , and . ESSDERC, page 102-105. IEEE, (2017)Resistive Coupled VO2 Oscillators for Image Recognition., , , , , and . ICRC, page 1-7. IEEE, (2018)Measurement of Nano-Displacement Based on In-Plane Suspended-Gate MOSFET Detection Compatible with a Front-End CMOS Process., , , , , , , , , and 1 other author(s). ISSCC, page 332-333. IEEE, (2008)Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance., , , , and . ESSDERC, page 161-164. IEEE, (2012)Impact of device geometry of the fin Electron-Hole Bilayer Tunnel FET., , , and . ESSDERC, page 307-310. IEEE, (2016)A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits., , , and . ICCAD, page 497-503. IEEE Computer Society / ACM, (2003)