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Leveraging spintronic devices for ultra-low power in-memory computing: Logic and neural network.

, , and . MWSCAS, page 1109-1112. IEEE, (2017)

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Efficient and Secure Deep Learning Inference System: A Software and Hardware Co-design Perspective.. Arizona State University, Tempe, USA, (2020)base-search.net (ftarizonastateun:item:62825).MRIMA: An MRAM-Based In-Memory Accelerator., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (5): 1123-1136 (2020)Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support., , , , , and . ACM Great Lakes Symposium on VLSI, page 347-352. ACM, (2021)Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System., , , , , and . ISQED, page 1-6. IEEE, (2022)ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator., , , , and . ISCAS, page 1-5. IEEE, (2021)SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network., , , , , , , , and . ICCD, page 417-424. IEEE, (2021)Optimize Deep Convolutional Neural Network with Ternarized Weights and High Accuracy., , and . WACV, page 913-921. IEEE, (2019)Parametric Noise Injection: Trainable Randomness to Improve Deep Neural Network Robustness against Adversarial Attack., , and . CoRR, (2018)Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping., , , , and . DAC, page 57. ACM, (2019)Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM., , and . ISVLSI, page 533-538. IEEE Computer Society, (2018)