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23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications., , , , , , , , , and 10 other author(s). ISSCC, page 392-393. IEEE, (2017)A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 380-382. IEEE, (2019)18.4 An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test scheme., , , , , , , , , and 9 other author(s). ISSCC, page 320-322. IEEE, (2016)A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller., , , , , , , , , and 19 other author(s). ISSCC, page 384-386. IEEE, (2019)18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface., , , , , , , , , and 12 other author(s). ISSCC, page 318-319. IEEE, (2016)High bandwidth memory(HBM) with TSV technique., , , , , , , , , and 9 other author(s). ISOCC, page 181-182. IEEE, (2016)A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy., , , , , , , , , and 15 other author(s). ISSCC, page 212-214. IEEE, (2018)A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications., , , , , , , , , and 11 other author(s). ISSCC, page 210-212. IEEE, (2018)The DSC Algorithm for Edge Detection., and . Australian Conference on Artificial Intelligence, volume 3339 of Lecture Notes in Computer Science, page 967-972. Springer, (2004)