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Discrete Migratory Bird Optimizer for Disassembly Line Balancing Problem Considering Tool Deterioration.

, , , , , and . ICNSC, page 1-6. IEEE, (2022)

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A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS., , , , and . VLSI Circuits, page 1-2. IEEE, (2020)A State-Equation-Based Backward Approach to a Legal Firing Sequence Existence Problem in Petri Nets., , , and . IEEE Trans. Syst. Man Cybern. Syst., 53 (8): 4968-4979 (2023)A Sub-0.01° Phase Resolution 6.8-mW fNIRS Readout Circuit Employing a Mixer-First Frequency-Domain Architecture., , , , , , , , , and 1 other author(s). ESSCIRC, page 229-232. IEEE, (2022)Weightings in Incremental ADCs: A Tutorial Review., , , , , , and . CICC, page 1-8. IEEE, (2023)A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing., , , , and . CICC, page 1-2. IEEE, (2022)A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling., , , , , and . ISCAS, page 1-5. IEEE, (2023)Matching User Accounts Across Social Networks Based on Users Message., , and . ICCS, volume 80 of Procedia Computer Science, page 2423-2427. Elsevier, (2016)Morph Resolution Based on Autoencoders Combined with Effective Context Information., , , and . ICCS (3), volume 10862 of Lecture Notes in Computer Science, page 487-498. Springer, (2018)A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation., , , , and . IEEE J. Solid State Circuits, 56 (8): 2375-2387 (2021)MMJN: Multi-Modal Joint Networks for 3D Shape Recognition., , , , and . ACM Multimedia, page 908-916. ACM, (2019)