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High performance mixed signal: Business and technology., , and . ESSCIRC, page 1-8. IEEE, (2010)A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications., , and . ESSCIRC, page 161-164. IEEE, (2005)BiCMOS and CMOS: a long term relation., and . ICECS, page 768-771. IEEE, (1996)Standard cell library tuning for variability tolerant designs., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Systematic power reduction and performance analysis of mismatch limited ADC designs., , and . ISLPED, page 78-83. ACM, (2005)A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS., , , and . IEEE J. Solid State Circuits, 43 (4): 778-786 (2008)A forward body bias generator for digital CMOS circuits with supply voltage scaling., , , , , , and . ISCAS, page 2482-2485. IEEE, (2010)A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior., , , , , and . ESSCIRC, page 464-467. IEEE, (2009)A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μm CMOS., , and . ESSCIRC, page 241-244. IEEE, (2003)A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR., , , and . CICC, page 329-332. IEEE, (2007)