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Disambiguation of "Chakradhar, Srimat T."

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MDR: performance model driven runtime for heterogeneous parallel platforms.

, , and . ICS, page 225-234. ACM, (2011)

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Chakradhar Narayan Sinha

T Masselink

T Neumann

T Attin

T Weber

 

Other publications of authors with the same name

Synchronous Test Generation Model for Asynchronous Circuits., , and . VLSI Design, page 178-185. IEEE Computer Society, (1996)Retiming with logic duplication transformation: theory and an application to partial scan., and . VLSI Design, page 296-302. IEEE Computer Society, (1996)A Test Function Architecture for Interconnected Finite State Machines., , and . VLSI Design, page 113-116. IEEE Computer Society, (1994)Zero Cost Test Point Insertion Technique for Structured ASICs., , , and . VLSI Design, page 357-363. IEEE Computer Society, (2007)Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip., , , , and . VLSI Design, page 65-70. IEEE Computer Society, (2005)Embedding Security in Wireless Embedded Systems., , and . VLSI Design, page 269-270. IEEE Computer Society, (2003)Computing approximately, and efficiently., , , and . DATE, page 748-751. ACM, (2015)Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets., , and . DATE, page 1296-1301. IEEE Computer Society, (2004)Unknown blocking scheme for low control data volume and high observability., , and . DATE, page 33-38. EDA Consortium, San Jose, CA, USA, (2007)ValuePack: value-based scheduling framework for CPU-GPU clusters., , , and . SC, page 53. IEEE/ACM, (2012)