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A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs., , , and . CoRR, (2022)Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest., , , , and . ISPD, page 256-264. ACM, (2023)A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts., , , and . ICCAD, page 69:1-69:9. ACM, (2022)From FPGAs to Obfuscated eASICs: Design and Security Trade-offs., , and . AsianHOST, page 1-4. IEEE, (2021)A Tutorial on Design Obfuscation: from Transistors to Systems.. LATS, page 1-3. IEEE, (2021)Resynthesis-based Attacks Against Logic Locking., , , , , and . ISQED, page 1-8. IEEE, (2023)CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks., , and . LATS, page 1-6. IEEE, (2024)Utilizing layout effects for analog logic locking., , , and . J. Cryptogr. Eng., 14 (2): 311-324 (June 2024)A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ., , , , and . NANOARCH, page 147-152. IEEE, (2017)Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2094-2107 (July 2023)