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A novel physical based model of deep-submicron CMOS transistors mismatch for Monte Carlo SPICE simulation.

, and . ISCAS (5), page 511-514. IEEE, (2001)

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A low voltage, 10-2550MHz, 0.15μ CMOS, process and divider modulus independent PLL using zero-VT MOSFETs.. ESSCIRC, page 105-108. IEEE, (2003)A novel physical based model of deep-submicron CMOS transistors mismatch for Monte Carlo SPICE simulation., and . ISCAS (5), page 511-514. IEEE, (2001)A novel SPICE behavioral macromodel of operational amplifiers including a high accuracy description of frequency characteristics., , , and . ISCAS (6), page 278-281. IEEE, (1999)Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs., , , , , and . ISCAS (4), page 766-769. IEEE, (2001)A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter., , , , , and . IEEE J. Solid State Circuits, 36 (11): 1673-1683 (2001)A 10Gb/s SiGe compact laser diode driver using push-pull emitter followers and miller compensated output switch.. ESSCIRC, page 557-560. IEEE, (2003)A sub-1.5°rms Phase-Noise Ring-Oscillator-Based Frequency Synthesizer for Low-IF Single-Chip DBS Satellite Tuner-Demodulator SoC., , and . ISSCC, page 2552-2561. IEEE, (2006)A Fully Integrated 0.13 µm CMOS Low-IF DBS Satellite Tuner Using Automatic Signal-Path Gain and Bandwidth Calibration., , , , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 897-921 (2007)A unified high accuracy behavioral SPICE macromodel of operational amplifiers featuring the frequency, temperature and power supply influences and the Monte Carlo simulation., and . ISCAS, page 697-700. IEEE, (2000)A DDFS Driven Mixing-DAC with Image and Harmonic Rejection Capabilities., , , , , and . ISSCC, page 372-373. IEEE, (2008)