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Disambiguation of "Tomishima, Shigeki"

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23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.

, , , , , , , , , , , , , , , , , , , and . ISSCC, page 404-405. IEEE, (2017)

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Shigeki Nagai

Shigeki Tomo

 

Other publications of authors with the same name

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology., , , , , , , , , and 2 other author(s). ISSCC, page 230-231. IEEE, (2014)23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache., , , , , , , , , and 10 other author(s). ISSCC, page 404-405. IEEE, (2017)Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs., , , , , and . IEEE J. Solid State Circuits, 30 (11): 1183-1188 (November 1995)SOI-DRAM circuit technologies for low power high speed multigiga scale memories., , , , , , and . IEEE J. Solid State Circuits, 31 (4): 586-591 (1996)A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test., , , , , , and . ITC, page 170-177. IEEE Computer Society, (2002)A 5.3-GB/s embedded SDRAM core with slight-boost scheme., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 34 (5): 661-669 (1999)A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs., , , , , , , , , and 11 other author(s). VLSIC, page 186-. IEEE, (2015)