( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.

, , , , , , , , , , , , , , , , , , , и . ISSCC, стр. 404-405. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Shelley Ching-yu Hsieh

Roxana Ching-Fan Hsieh Pung

Wilhelm Ching

Paisal Chingduang

Ching-Ching Pan

 

Другие публикации лиц с тем же именем

An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (3): 410-424 (1993)An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation., , , и . DAC, стр. 481-486. ACM, (1991)LiB: A Cell Layout Generator., , , и . DAC, стр. 474-479. IEEE Computer Society Press, (1990)23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 404-405. IEEE, (2017)An optimal transistor-chaining algorithm for CMOS cell layout., , , и . ICCAD, стр. 344-347. IEEE Computer Society, (1989)