( en | de | ru )

 

Disambiguation of "Wunderlich, Hans-Joachim"

Author of the publication

copydeleteadd this publication to your clipboard
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.

, , and . DDECS, page 185-190. IEEE Computer Society, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hans-Joachim Wunderlich

Hans-Joachim Wunderlich

Hans-Joachim Wunderlich

Joachim Wunderlich

Joachim Wunderlich

 

Other publications of authors with the same name

Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits., and . FTCS, page 36-41. IEEE Computer Society, (1988)Tools and devices supporting the pseudo-exhaustive test., and . EURO-DAC, page 13-17. IEEE Computer Society, (1990)Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms., , , and . EDCC, volume 1667 of Lecture Notes in Computer Science, page 339-350. Springer, (1999)ETS 2015 best paper., and . ETS, page 1. IEEE, (2016)Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses., , , , and . ITC, page 1-10. IEEE, (2019)Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm., , , , and . DSN-W, page 195-198. IEEE, (2023)Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication., , and . DSN-W, page 203-206. IEEE, (2023)Deterministic Pattern Generation for Weighted Random Pattern Testing., and . ED&TC, page 30-36. IEEE Computer Society, (1996)SWIFT: Switch-Level Fault Simulation on GPUs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (1): 122-135 (2019)Built-In Test for Hidden Delay Faults., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1956-1968 (2019)