Author of the publication

HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs.

, , , and . ICCD, page 470-476. IEEE Computer Society, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An integrated floorplanning with an efficient buffer planning algorithm., , , , , , and . ISPD, page 136-142. ACM, (2003)Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List., , , , , and . DAC, page 770-775. ACM, (2001)Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs., , , , , and . Integr., 46 (1): 1-9 (2013)Novel and efficient min cut based voltage assignment in gate level., , , , , and . ISQED, page 150-155. IEEE, (2011)VLSI floorplanning with boundary constraints based on corner block list., , , , , and . ASP-DAC, page 509-514. ACM, (2001)LP based white space redistribution for thermal via planning and performance optimization in 3D ICs., , , , and . ASP-DAC, page 209-212. IEEE, (2008)Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs., , , , , and . ASP-DAC, page 261-266. IEEE, (2011)An effective buffer planning algorithm for IP based fixed-outline SOC placement., , , , and . ACM Great Lakes Symposium on VLSI, page 564-569. ACM, (2007)Incremental layout optimization for NoC designs based on MILP formulation., , , and . ASICON, page 357-360. IEEE, (2011)Fine grain 3D integration for microarchitecture design through cube packing exploration., , , , and . ICCD, page 259-266. IEEE, (2007)