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Design-for-testability for embedded delay-locked loops.

, and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 984-988 (2005)

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Verification of Embedded Phase-Locked Loops., and . ISQED, page 290-295. IEEE Computer Society, (2001)Design-for-testability for embedded delay-locked loops., and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 984-988 (2005)