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Disambiguation of "Samori, Carlo"

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Background adaptive linearization of high-speed digital-to-analog Converters.

, , , and . ISCAS, page 582-585. IEEE, (2013)

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Paolo Samorí

Lothar Carlowitz

Teresa Carlomagno

Horst Carlowitz

Hans Carlowitz

 

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Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band., , , and . ISSCC, page 50-51. IEEE, (2010)Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 200-204 (2011)EP2: Lost art? Analog tricks and techniques from the masters., , and . ISSCC, page 1. IEEE, (2015)A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity., , , and . ICECS, page 1-4. IEEE, (2021)Time-to-digital converter with 3-ps resolution and digital linearization algorithm., , , , and . ESSCIRC, page 262-265. IEEE, (2010)Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers., , , , , and . ISCAS, page 1-4. IEEE, (2018)A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters., , , , , , , , and . NEWCAS, page 20-24. IEEE, (2022)2.9 A Background calibration technique to control bandwidth in digital PLLs., , , and . ISSCC, page 54-55. IEEE, (2014)10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM., , , , , , , and . ISSCC, page 188-190. IEEE, (2024)5-GHz in-phase coupled oscillators with 39% tuning range., , , , and . CICC, page 269-272. IEEE, (2004)