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A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro., и . Intelligent Memory Systems, том 2107 из Lecture Notes in Computer Science, стр. 1-14. Springer, (2000)Split capacitor DAC mismatch calibration in successive approximation ADC., , , , , , , , , и 2 other автор(ы). CICC, стр. 279-282. IEEE, (2009)A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX., , , , , , , , , и . ISSCC, стр. 224-598. IEEE, (2007)A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 168-169. IEEE, (2010)A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS., , , , , , , , , и 8 other автор(ы). ISSCC, стр. 360-361. IEEE, (2009)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , и . CICC, стр. 131-134. IEEE, (2005)A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique., , , , , , , , и . IEEE J. Solid State Circuits, 40 (8): 1680-1687 (2005)A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS., , , , , и . IEEE J. Solid State Circuits, 40 (4): 986-993 (2005)500-Mb/s nonprecharged data bus for high-speed DRAM's., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 33 (11): 1720-1730 (1998)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC., , , , , , , , , и 2 other автор(ы). IEICE Trans. Electron., 93-C (3): 295-302 (2010)