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Optimization of Master-Slave Flip-Flops for High-Performance Applications.

, , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 439-449. Springer, (2006)

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Inertial and degradation delay model for CMOS logic gates., , , , and . ISCAS, page 459-462. IEEE, (2000)SODS: a new CMOS differential-type structure., , , , and . IEEE J. Solid State Circuits, 30 (7): 835-838 (July 1995)A switching noise vision of the optimization techniques for low-power synthesis., , , and . ECCTD, page 156-159. IEEE, (2007)Low-Power Differential Logic Gates for DPA Resistant Circuits., , and . DSD, page 671-674. IEEE Computer Society, (2014)Degradation Delay Model Extension to CMOS Gates., , , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 149-158. Springer, (2000)A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch., , , , , and . ISCAS, page 2019-2022. IEEE, (1993)HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model., , , , and . DATE, page 467-471. IEEE Computer Society, (2001)Analog/mixed-signal IP modeling for design reuse., , , and . DATE, page 766-767. IEEE Computer Society, (2001)ASIC-in-the-loop methodology for verification of piecewise affine controllers., , , , , and . ICECS, page 388-391. IEEE, (2012)Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions., , , , and . Int. J. Circuit Theory Appl., 44 (1): 4-20 (2016)