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Disambiguation of "Arakida, Hideho"

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A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme.

, , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 33 (11): 1772-1780 (1998)

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A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 33 (11): 1772-1780 (1998)Comparing memory systems for chip multiprocessors., , , , , and . ISCA, page 358-368. ACM, (2007)Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques., , , , , , , , and . DAC, page 483-488. ACM Press, (1998)A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme., , , , , , , , , and . CICC, page 495-498. IEEE, (1998)A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm., , , , , , , , , and 4 other author(s). ISSCC, page 326-327. IEEE, (2010)A Single-Chip Low-Power Mpeg-4 Audiovisual Lsi Using Embedded Dram Technology., , , and . ICME, IEEE Computer Society, (2001)Design and implementation of scalable, transparent threads for multi-core media processor., , , , , , , , , and 3 other author(s). DATE, page 1035-1039. IEEE, (2009)A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications., , , , , , , , , and 7 other author(s). ISCAS, page 188-191. IEEE, (2000)Comparative evaluation of memory models for chip multiprocessors., , , , , and . ACM Trans. Archit. Code Optim., 5 (3): 12:1-12:30 (2008)Visconti2 - a heterogeneous multi-core SoC for image-recognition applications., , , , , and . Hot Chips Symposium, page 1-22. IEEE, (2012)