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Disambiguation of "Reisis, Dionysios I."

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SDN control framework with dynamic resource assignment for slotted optical datacenter networks.

, , , , , , , , , , , and . OFC, page 1-2. IEEE, (2017)

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Dionysios Chalkomatas

Dionysios Basdekis

Dionysios Gliatis

Dionysios Logothetis

Dionysios Antonopulos

 

Other publications of authors with the same name

Using high-level synthesis to build memory and datapath optimized DSP accelerators., , and . ICECS, page 714-717. IEEE, (2014)Towards sharing one FPGA SoC for both low-level PHY and high-level AI/ML computing at the edge., , , , , and . MeditCom, page 76-81. IEEE, (2021)An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems., , , , , and . ICECS, page 93-96. IEEE, (1999)Image computations on reconfigurable VLSI arrays., , , and . CVPR, page 925-930. IEEE, (1988)Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators., and . VLSI Signal Processing, 35 (2): 179-186 (2003)End-to-End Real-Time Service Provisioning over a SDN-controllable 60 GHz analog FiWi X-haul for 5G Hot-Spot Networks., , , , , , , , , and 17 other author(s). OFC, page 1-3. IEEE, (2022)Parallel Memory Accessing for FFT Architectures., , , and . J. Signal Process. Syst., 90 (11): 1593-1607 (2018)Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification., , , and . J. Imaging, 8 (4): 114 (2022)NEPHELE: Vertical Integration and Real-Time Demonstration of an Optical Datacenter Network., , , , , and . ICTON, page 1-4. IEEE, (2018)A configurable length, Fused Multiply-Add floating point unit for a VLIW processor., , and . SoCC, page 93-96. IEEE, (2009)