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Disambiguation of "Levantino, Salvatore"

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A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power.

, , , and . ISSCC, page 342-344. IEEE, (2012)

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Salvatore Loiero

Fundamentalmetanoia: Untersuchungen zu einem Ort eschato-praktischer Erfahrungs- und Erinnerungskultur. Uni Tübingen, habilitation, (2009)

Salvatore Cusenza

Salvatore Saputo

Salvatore Scarlata

Salvatore Chiantia

 

Other publications of authors with the same name

Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band., , , and . ISSCC, page 50-51. IEEE, (2010)Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 200-204 (2011)Time-to-digital converter with 3-ps resolution and digital linearization algorithm., , , , and . ESSCIRC, page 262-265. IEEE, (2010)10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM., , , , , , , and . ISSCC, page 188-190. IEEE, (2024)2.9 A Background calibration technique to control bandwidth in digital PLLs., , , and . ISSCC, page 54-55. IEEE, (2014)Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers., , , , , and . ISCAS, page 1-4. IEEE, (2018)A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique., , and . ISCAS, page 1-4. IEEE, (2018)A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters., , , , , , , , and . NEWCAS, page 20-24. IEEE, (2022)Bang-bang digital PLLs.. ESSCIRC, page 329-334. IEEE, (2016)A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power., , , and . ISSCC, page 342-344. IEEE, (2012)