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Signal Delay in General RC Networks.

T. Lin, и C. Mead. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 3 (4): 331-349 (1984)

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Signal Delay in General RC Networks.T. Lin, и C. Mead. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 3 (4): 331-349 (1984)A VLSI Approach to Sound Synthesis.J. Wawrzynek, C. Mead, T. Lin, H. Liu, и L. Dyer. ICMC, Michigan Publishing, (1984)A Hierarchical Timing Simulation Model.T. Lin, и C. Mead. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 5 (1): 188-197 (1986)A Hierarchical Timing Simulation Model for Digital Integrated Circuits and Systems.T. Lin. California Institute of Technology, USA, (1985)