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3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).

K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, and H. Iwai. ASICON, page 1137-1140. IEEE, (2017)

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Wataru Kobayashi

Kaku Saito

Itohei Saito

Mitsuhiro Saito

Naoki Saito

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A Low Noise 8Mpixel CMOS Image Sensor with 5.36GHz Global Counter and Dual Latch Skew Canceler for Surveillance AI Camera System.Y. Iizuka, A. Maezono, W. Saito, A. Yamane, K. Takami, and F. Morishita. A-SSCC, page 1-3. IEEE, (2023)3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito and 12 other author(s). ASICON, page 1137-1140. IEEE, (2017)IGBT Power Module Design for Suppressing Gate Voltage Spike at Digital Gate Control.Z. Lou, T. Mamee, K. Hata, M. Takamiya, S. Nishizawa, and W. Saito. IEEE Access, (2023)GaN MIS-HEMTs in Repetitive Overvoltage Switching: Parametric Shift and Recovery.Q. Song, J. Kozak, Y. Ma, J. Liu, R. Zhang, R. Volkov, D. Sherman, K. Smith, W. Saito, and Y. Zhang. IRPS, page 10. IEEE, (2022)Switching of 3300V Scaled IGBT by 5V Gate Drive.T. Hiramoto, K. Satoh, T. Matsudai, W. Saito, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi and 13 other author(s). ASICON, page 1-3. IEEE, (2019)Accelerating the Recovery of p-Gate GaN HEMTs after Overvoltage Stresses.J. Kozak, Q. Song, J. Liu, R. Zhang, Q. Li, W. Saito, and Y. Zhang. IRPS, page 22-1. IEEE, (2022)An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image Sensor.F. Morishita, M. Otsuka, and W. Saito. ATS, page 1-6. IEEE, (2020)A Low Noise and Linearity Improvement CMOS Image Sensor for Surveillance Camera with Skew-Relaxation Local Multiply Circuit and On-Chip Testable Ramp Generator.W. Saito, Y. Iizuka, N. Kato, R. Otake, and F. Morishita. A-SSCC, page 1-3. IEEE, (2021)UIS test of high-voltage GaN-HEMTs with p-type gate structure.W. Saito, and T. Naka. Microelectron. Reliab., (2016)

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Disambiguation of "Saito, Wataru"

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URL
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Chicago
DIN 1505
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3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).

Please choose a person to relate this publication to

Wataru Kobayashi

Kaku Saito

Itohei Saito

Mitsuhiro Saito

Naoki Saito

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Saito, Wataru"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).

Please choose a person to relate this publication to

Wataru Kobayashi

Kaku Saito

Itohei Saito

Mitsuhiro Saito

Naoki Saito

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).