Author of the publication

Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture.

, , , , , , , and . ICCAD, page 8:1-8:9. ACM, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain., , , , , , , , , and 5 other author(s). CoRR, (2018)C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing., , , and . ESSCIRC, page 131-134. IEEE, (2019)Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2)., , , and . ACM J. Emerg. Technol. Comput. Syst., 15 (4): 31:1-31:2 (2019)Benchmarking TinyML Systems: Challenges and Direction., , , , , , , , , and 7 other author(s). CoRR, (2020)Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions., , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (1): 6-27 (2018)XST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning., , , , , and . DATE, page 48-51. IEEE, (2022)Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing., , , , , , and . IRPS, page 1-7. IEEE, (2021)Towards a Wearable Cough Detector Based on Neural Networks., , , , , , , , , and 3 other author(s). ICASSP, page 2161-2165. IEEE, (2018)Ranking the parameters of deep neural networks using the fisher information., , , , and . ICASSP, page 2647-2651. IEEE, (2016)A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI., , , , , , , and . ISSCC, page 400-401. IEEE, (2013)