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Disambiguation of "Jayapala, Murali"

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Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.

, , , and . ASP-DAC/VLSI Design, page 338-344. IEEE Computer Society, (2002)

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Aarthi Murali

Murali Sukumaran

Kota Murali

Murali Krishna Bollepalli

NULL Murali Dama

 

Other publications of authors with the same name

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 151-155 (2009)EMPIRE: Empirical power/area/timing models for register files., , , , and . Microprocess. Microsystems, 33 (4): 295-300 (2009)Instruction Buffering Exploration for Low Energy Embedded Processors., , , , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 409-419. Springer, (2003)A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors., , , , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 258-267. Springer, (2002)Instruction Transfer And Storage Exploration for Low Energy VLIWs., , , , and . SiPS, page 292-297. IEEE, (2006)Low Power Coarse-Grained Reconfigurable Instruction Set Processor., , , , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 230-239. Springer, (2003)Intra-operative Brain Tumor Detection with Deep Learning-Optimized Hyperspectral Imaging., , , , , , , , , and 2 other author(s). CoRR, (2023)Design Style Case Study for Embedded Multi Media Compute Nodes., , , , , , , , , and 4 other author(s). RTSS, page 104-113. IEEE Computer Society, (2004)Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors., , , and . ASP-DAC/VLSI Design, page 338-344. IEEE Computer Society, (2002)L0 buffer energy optimization through scheduling and exploration., , , , , and . SAC, page 905-906. ACM, (2004)