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timing models for register files.

P. Raghavan, A. Lambrechts, M. Jayapala, F. Catthoor, and D. Verkest. Microprocess. Microsystems, 33 (4): 295-300 (2009)

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Raghavan Vallur

Praveen Konidala

Paurush Praveen

Sarada Raghavan

Raghavan Chinnadurai

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Dimensioning for power and performance under 10nm: The limits of FinFETs scaling.M. Bardon, P. Schuddinck, P. Raghavan, D. Jang, D. Yakimets, A. Mercha, D. Verkest, and A. Thean. ICICDT, page 1-4. IEEE, (2015)Modeling FinFET metal gate stack resistance for 14nm node and beyond.K. Miyaguchi, B. Parvais, L. Ragnarsson, P. Wambacq, P. Raghavan, A. Mercha, A. Mocuta, D. Verkest, and A. Thean. ICICDT, page 1-4. IEEE, (2015)Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals.T. Schuster, B. Bougard, P. Raghavan, R. Priewasser, D. Novo, L. der Perre, and F. Catthoor. SAMOS, volume 4599 of Lecture Notes in Computer Science, page 322-332. Springer, (2007)A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.P. Raghavan, S. Munaga, E. Ramos, A. Lambrechts, M. Jayapala, F. Catthoor, and D. Verkest. ARCS, volume 4415 of Lecture Notes in Computer Science, page 57-68. Springer, (2007)Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs.R. Patel, K. Xu, E. Friedman, and P. Raghavan. ACM Great Lakes Symposium on VLSI, page 233-238. ACM, (2016)Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.H. Kükner, P. Weckx, S. Morrison, J. Franco, M. Toledano-Luque, M. Cho, P. Raghavan, B. Kaczer, D. Jang, K. Miyaguchi and 5 other author(s). Microprocess. Microsystems, 39 (8): 1039-1051 (2015)A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency.R. Fasthuber, P. Raghavan, L. der Perre, and F. Catthoor. IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 1973-1986 (2015)System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.P. Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. der Perre, E. Beyne, and R. Varadarajan. IEEE Embed. Syst. Lett., 6 (4): 85-88 (2014)Bias Temperature Instability analysis of FinFET based SRAM cells.S. Khan, I. Agbo, S. Hamdioui, H. Kukner, B. Kaczer, P. Raghavan, and F. Catthoor. DATE, page 1-6. European Design and Automation Association, (2014)Resolving the memory bottleneck for single supply near-threshold computing.T. Gemmeke, M. Sabry, J. Stuijt, P. Raghavan, F. Catthoor, and D. Atienza. DATE, page 1-6. European Design and Automation Association, (2014)

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Disambiguation of "Raghavan, Praveen"

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EMPIRE: Empirical power/area/timing models for register files.

Please choose a person to relate this publication to

Raghavan Vallur

Praveen Konidala

Paurush Praveen

Sarada Raghavan

Raghavan Chinnadurai

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Raghavan, Praveen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML EMPIRE: Empirical power/area/timing models for register files.

Please choose a person to relate this publication to

Raghavan Vallur

Praveen Konidala

Paurush Praveen

Sarada Raghavan

Raghavan Chinnadurai

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

EMPIRE: Empirical power/area/timing models for register files.