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Disambiguation of "Dosaka, Katsumi"

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Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.

, , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (8): 1312-1315 (2007)

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Katsumi Nomura

 

Other publications of authors with the same name

A 40GOPS 250mW massively parallel processor based on matrix architecture., , , , , , , , , and 2 other author(s). ISSCC, page 1616-1625. IEEE, (2006)A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM., , , and . CICC, page 451-454. IEEE, (2005)CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table image coding example., , , , , , , and . ISCAS (5), page 5202-5205. IEEE, (2005)Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine., , , , , , , and . ISCAS, page 525-528. IEEE, (2007)A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI., , , , , and . CICC, page 429-432. IEEE, (2006)Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (8): 1312-1315 (2007)Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (1): 334-345 (2007)Design methodology of embedded DRAM with virtual-socket architecture., , , , , , , and . IEEE J. Solid State Circuits, 36 (1): 46-54 (2001)A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI., , , , , , , , and . IEICE Trans. Electron., 90-C (4): 765-771 (2007)Design methodology of the embedded DRAM with the virtual socket architecture., , , , and . CICC, page 271-274. IEEE, (2000)