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Disambiguation of "Iwasaki, Kazuhiko"

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Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.

, , , , , , , , and . Asian Test Symposium, page 28-31. IEEE Computer Society, (2003)

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Kazuhiko Yoshida

Kazuhiko Yoshida

Kazuhiko Sano

Kazuhiko Uzawa

Kazuhiko Yoshida

 

Other publications of authors with the same name

On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers., , , and . IEEE Trans. Computers, 44 (11): 1265-1274 (1995)Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test., , , , and . J. Low Power Electron., 5 (4): 520-528 (2009)Reduction of Area per Good Die for SoC Memory Built-In Self-Test., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2463-2471 (2010)Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters., , , , and . Asian Test Symposium, page 190-195. IEEE Computer Society, (2004)Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage., , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (2012)Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing.. Syst. Comput. Jpn., 21 (5): 29-38 (1990)Aliasing Probabilities and Weight Distributions of Several Codes., and . Syst. Comput. Jpn., 20 (9): 81-88 (1989)Analysis of Probabilistic Trapezoid Protocol for Data Replication., , , , and . DSN, page 782-791. IEEE Computer Society, (2005)Analysis and proposal of signature circuits for LSI testing.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (1): 84-90 (1988)Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation., , and . ITC, page 1-8. IEEE, (2017)