Author of the publication

The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 846-852 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP Processor., , , and . SoCC, page 217-220. IEEE, (2006)The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 42 (4): 846-852 (2007)A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 42 (1): 17-25 (2007)The Organization of Expert Systems, A Tutorial., , , , , , and . Artif. Intell., 18 (2): 135-173 (1982)Retrospective on "The Organization of Expert Systems, a Tutorial"., , , , , , and . Artif. Intell., 59 (1-2): 221-224 (1993)A survey of current paradigms in machine translation., , and . Advances in Computers, (1999)A first-pass approach for evaluating machine translation systems., , and . Mach. Transl., 8 (1-2): 49-58 (1993)SAPS: A Production System with Active Data Structures.. IEEE Expert, 5 (6): 28-33 (1990)Ontologies for supporting engineering analysis models., , and . Artif. Intell. Eng. Des. Anal. Manuf., 19 (1): 1-18 (2005)