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FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing.

, , , , , и . ASAP, стр. 29-32. IEEE, (2020)

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Ryukyo Nitta

Suteera Nittayananta

 

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A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI., , , , и . IEEE Trans. Consumer Electronics, 45 (4): 1130-1133 (1999)Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture., , , , , , , и . COOL CHIPS, стр. 1-3. IEEE, (2019)Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture., , и . IEICE Trans. Commun., 103-B (1): 11-19 (2020)A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation., , и . IEICE Trans. Commun., 104-B (5): 481-489 (2021)OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization., , , , , , , и . MWSCAS, стр. 1-4. IEEE, (2022)An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture., , , , , , , и . COOL CHIPS, стр. 1-3. IEEE, (2022)Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level., , , , , , , , , и 1 other автор(ы). DATE, стр. 20002-20007. IEEE Computer Society, (2003)Video Service Function Chaining with a Real-time Packet Reordering Circuit., , и . ISCAS, стр. 1-5. IEEE, (2018)FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing., , , , , и . ASAP, стр. 29-32. IEEE, (2020)Motion Estimation and Compensation Hardware Architecture with Hierarchy of Flexibility in Video Encoder LSIs.. Kyoto University, Japan, (2015)