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A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography.

, , , , and . ASP-DAC, page 637-644. IEEE, (2010)

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Double patterning layout decomposition for simultaneous conflict and stitch minimization., , and . ISPD, page 107-114. ACM, (2009)Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner., and . ISQED, page 352-356. IEEE Computer Society, (2008)Overlay aware interconnect and timing variation modeling for double patterning technology., and . ICCAD, page 488-493. IEEE Computer Society, (2008)Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper)., , , , , , , and . ICCAD, page 240-242. ACM, (2012)Chemical-mechanical polishing aware application-specific 3D NoC design., , , and . ICCAD, page 207-212. IEEE Computer Society, (2011)Stress-driven 3D-IC placement with TSV keep-out zone and regularity study., , , , and . ICCAD, page 669-674. IEEE, (2010)Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis., , , , and . ISQED, page 344-347. IEEE Computer Society, (2003)Design for manufacturability and reliability for TSV-based 3D ICs., , , , , , , and . ASP-DAC, page 750-755. IEEE, (2012)A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography., , , , and . ASP-DAC, page 637-644. IEEE, (2010)Layout aware line-edge roughness modeling and poly optimization for leakage minimization., and . DAC, page 447-452. ACM, (2011)