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Disambiguation of "Karunaratne, Geethan"

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High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension.

, , , , , , , , , , and . ASAP, page 164-169. IEEE Computer Society, (2017)

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Pasan Karunaratne

 

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Deep learning acceleration based on in-memory computing., , , , , , , , , and 7 other author(s). IBM J. Res. Dev., 63 (6): 7:1-7:16 (2019)HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing., , , , , , , , , and 14 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning., , , , , , , and . ISCAS, page 1-5. IEEE, (2020)In-memory Vector Symbolic Architectures.. ETH Zurich, Zürich, Switzerland, (2023)base-search.net (ftethz:oai:www.research-collection.ethz.ch:20.500.11850/625319).Real-time Language Recognition using Hyperdimensional Computing on Phase-change Memory Array., , , , and . AICAS, page 1. IEEE, (2021)Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing., , , , , and . IJCNN, page 1-8. IEEE, (2022)Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH)., , , , , , , , , and 12 other author(s). CF, page 191-193. ACM, (2021)Decoding Superpositions of Bound Symbols Represented by Distributed Representations., , , , and . NeSy, volume 3432 of CEUR Workshop Proceedings, page 279-288. CEUR-WS.org, (2023)Constrained Few-shot Class-incremental Learning., , , , , and . CVPR, page 9047-9057. IEEE, (2022)Applications of Computation-In-Memory Architectures based on Memristive Devices., , , , , , , , , and 3 other author(s). DATE, page 486-491. IEEE, (2019)