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An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories., , and . ASICON, page 1-4. IEEE, (2015)Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory., , and . IOLTS, page 226-227. IEEE, (2018)Fault-tolerance design of memory systems based on DBL structures., and . APCCAS (1), page 221-224. IEEE, (2002)ECC Caching Techniques for Protecting NAND Flash Memories., , , and . ITC-Asia, page 47-52. IEEE, (2020)Fault Securing Techniques for Yield and Reliability Enhancement of RRAM., , and . ATS, page 13-18. IEEE, (2022)Fault Scrambling Techniques for Yield Enhancement of Embedded Memories., , , , and . Asian Test Symposium, page 215-220. IEEE Computer Society, (2013)Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories., , , and . ATS, page 254-259. IEEE Computer Society, (2017)Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs., , , , and . ATS, page 242-247. IEEE Computer Society, (2017)Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories., , and . ATS, page 287-292. IEEE Computer Society, (2016)Built-In Self-Repair Techniques for Heterogeneous Memory Cores., , and . PRDC, page 69-74. IEEE Computer Society, (2009)