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Disambiguation of "Hsu, Chun-Lung"

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ECC Caching Techniques for Protecting NAND Flash Memories.

, , , and . ITC-Asia, page 47-52. IEEE, (2020)

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Chun-Chen Hsu

Chun-Ting Hsu

Chun-Ming Hsu

Barbara Lung

Andreas Lung

 

Other publications of authors with the same name

ECC Caching Techniques for Protecting NAND Flash Memories., , , and . ITC-Asia, page 47-52. IEEE, (2020)Novel Built-In Current-Sensor-Based IDDQ Testing Scheme for CMOS Integrated Circuits., , and . IEEE Trans. Instrumentation and Measurement, 58 (7): 2196-2208 (2009)Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM., , , , , , , and . Asian Test Symposium, page 123-127. IEEE Computer Society, (2013)Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications., , , and . DFT, page 136-143. IEEE Computer Society, (2010)A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip., and . DFT, page 122-128. IEEE Computer Society, (2010)High-performance 3D-SRAM architecture design., and . APCCAS, page 907-910. IEEE, (2010)Design of Low-Frequency Low-Pass Filters for Biomedical Applications., , , and . APCCAS, page 690-695. IEEE, (2006)Testing stuck-open faults of priority address encoder in content addressable memories., , , and . ASP-DAC, page 347-351. ACM, (2019)Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs., , , , , , and . Asian Test Symposium, page 107-108. IEEE Computer Society, (2013)A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs., , , , and . 3DIC, page 1-3. IEEE, (2019)