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Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (11): 1454-1464 (2008)

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Low-latency software LDPC decoders for x86 multi-core devices., and . SiPS, page 1-6. IEEE, (2017)Software polar decoder on an embedded processor., , and . SiPS, page 180-185. IEEE, (2014)Hardware Virtual Components Compliant with Communication System Standards., , , , , , , and . DSD, page 88-95. IEEE Computer Society, (2005)Methodology to Adapt Neural Network on Constrained Device at Topology level., , , , , and . SiPS, page 1-6. IEEE, (2022)An LP-based algorithm for decoding terminated LDPC convolutional codes., , , , and . IINTEC, page 95-100. IEEE, (2017)Multicore implementation of LDPC decoders based on ADMM algorithm., , , , and . ICASSP, page 971-975. IEEE, (2016)High data rate and flexible hardware QC-LDPC decoder for satellite optical communications., , , and . ISTC, page 1-5. IEEE, (2018)An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes., , , , and . LCPC, volume 9519 of Lecture Notes in Computer Science, page 303-317. Springer, (2015)High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices., , and . DASIP, volume 13425 of Lecture Notes in Computer Science, page 3-15. Springer, (2022)High-level synthesis for the design of FPGA-based signal processing systems., and . ICSAMOS, page 25-32. IEEE, (2009)